Low-Cost Electronic Project of RF Synthesizer Uses Generic ICs. You can design a hardware-based frequency synthesizer with one
inexepensive IC and a few passive components. Such synthesizer chips are
not always available, however, because they are typically
single-sourced and are not in stock with parts distributors. The need
for a working circuit in a short time and using common parts prompted
the creation of the circuit in this Design Idea. The synthesizer covers
the US commercial AM (amplitude-modulation) broadcast band. It tunes in
10-kHz steps from 500 to 1800 kHz, but you can scale the frequencies for
other applications.
The PLL (phase-locked loop) time base is a 100-kHz, tuning-fork-cut crystal of the same size as those in wrist watches. Using a more common crystal requires some extra parts to scale the frequency. Note that if you attempt to use one of these tiny crystals with a CMOS gate oscillator circuit, however, the circuit will either fail to start or exhibit visible jitter. A discrete-transistor Franklin oscillator, such as the one comprising Q3 and Q4 works better (Figure 1). This circuit also works well in the VCO (voltage-controlled-oscillator) portion of the synthesizer.
RF Synthesizer Uses Generic ICs Circuit Diagram:
You use IC4A, one-half of a 74HC390 dual decade-divider IC, to divide the 100-kHz reference into the 10-kHz frequency that the PLL uses. This 10-kHz square wave feeds one input of the phase comparator, IC3, and drives a voltage tripler circuit comprising D12 through D15. This tripler creates approximately 12V and obviates the need for a second higher-voltage power rail. You need the 12V to bias the VCO’s varactor diode to the top of its tuning range.
The VCO, comprising Q1 and Q2, runs at twice the desired output frequency. Varactor diode D1 and inductor L1 provide a tunable tank circuit. Any varactor for AM-radio tuning should work. The capacitance of these diodes varies from 500 pF with no dc bias to 25 pF with a 12V reverse bias. IC1A divides the LC oscillator by two to yield a symmetrical output waveform.
IC2 further divides the VCO to the PLL’s frequency. IC2, an eight-stage binary counter, resets itself to zero when it reaches the desired count. IC1B, a pulsestretching one-shot, ensures that all sections of IC2 reset at the target count. You program the divider with DIP switch S1. Diodes D2 through D9 supply the necessary AND-logic function.
To set the synthesizer frequency, you first calculate the required divisor. For a 1140-kHz output, you must divide the VCO by 114 to equal the PLL’s frequency of 10 kHz. You can close the DIP switches in S1 – in this case, switches 64, 32, 16, and 2 – so that the numbers add up to the divisor: 114.
The PLL comparator is a three-state phase and frequency detector (Reference 1). When the divided VCO frequency is greater than 10 kHz, the Q output of IC3B goes high and the Q output of IC3A pulses at a 10-kHz rate. This action turns on Q6, back-biasing D16 to create a high-impedance state with respect to the 12V supply. Loop-filter capacitor C2 then discharges through R15 and Q5. When the divided VCO is lower than the loop frequency, the Q output of IC3A goes low, turning off Q5 and creating a high-impedance state with respect to ground. Q6 now pulses on and off, allowing C2 to charge through D15 and R16. At PLL lock, Q5 is off and Q6 is on, except for a narrow “keep-alive” pulse at the loop frequency.
Reference
The PLL (phase-locked loop) time base is a 100-kHz, tuning-fork-cut crystal of the same size as those in wrist watches. Using a more common crystal requires some extra parts to scale the frequency. Note that if you attempt to use one of these tiny crystals with a CMOS gate oscillator circuit, however, the circuit will either fail to start or exhibit visible jitter. A discrete-transistor Franklin oscillator, such as the one comprising Q3 and Q4 works better (Figure 1). This circuit also works well in the VCO (voltage-controlled-oscillator) portion of the synthesizer.
RF Synthesizer Uses Generic ICs Circuit Diagram:
You use IC4A, one-half of a 74HC390 dual decade-divider IC, to divide the 100-kHz reference into the 10-kHz frequency that the PLL uses. This 10-kHz square wave feeds one input of the phase comparator, IC3, and drives a voltage tripler circuit comprising D12 through D15. This tripler creates approximately 12V and obviates the need for a second higher-voltage power rail. You need the 12V to bias the VCO’s varactor diode to the top of its tuning range.
The VCO, comprising Q1 and Q2, runs at twice the desired output frequency. Varactor diode D1 and inductor L1 provide a tunable tank circuit. Any varactor for AM-radio tuning should work. The capacitance of these diodes varies from 500 pF with no dc bias to 25 pF with a 12V reverse bias. IC1A divides the LC oscillator by two to yield a symmetrical output waveform.
IC2 further divides the VCO to the PLL’s frequency. IC2, an eight-stage binary counter, resets itself to zero when it reaches the desired count. IC1B, a pulsestretching one-shot, ensures that all sections of IC2 reset at the target count. You program the divider with DIP switch S1. Diodes D2 through D9 supply the necessary AND-logic function.
To set the synthesizer frequency, you first calculate the required divisor. For a 1140-kHz output, you must divide the VCO by 114 to equal the PLL’s frequency of 10 kHz. You can close the DIP switches in S1 – in this case, switches 64, 32, 16, and 2 – so that the numbers add up to the divisor: 114.
The PLL comparator is a three-state phase and frequency detector (Reference 1). When the divided VCO frequency is greater than 10 kHz, the Q output of IC3B goes high and the Q output of IC3A pulses at a 10-kHz rate. This action turns on Q6, back-biasing D16 to create a high-impedance state with respect to the 12V supply. Loop-filter capacitor C2 then discharges through R15 and Q5. When the divided VCO is lower than the loop frequency, the Q output of IC3A goes low, turning off Q5 and creating a high-impedance state with respect to ground. Q6 now pulses on and off, allowing C2 to charge through D15 and R16. At PLL lock, Q5 is off and Q6 is on, except for a narrow “keep-alive” pulse at the loop frequency.
Reference
- Shahriary, I, G Des Brisay, S Avery, and P Gibsan, “GaAs Monolithic Phase/Frequency Discriminator,” IEEE GaAs Symposium, 1985, pg 183.
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